The present invention generally relates to a semiconductor device and more particularly, to an improvement on an interconnection for a semiconductor device.
Recently, there has been remarkable progress in the field of semiconductor techniques, particularly, with respect to DRAM (Dynamic Random Access Memory) techniques which leads to improvements in silicon (Si) LSI (Large Scale Integration) techniques wherein a 4M DRAM will be put into actual application in the near future. Such VLSI is based on an MOS (Metal Oxide Semiconductor) technology using a process technology on the order of about 2 m to 1 m as a level for fine-pattern fabrication technology. A process technology along the order of a sub-micron region has already been brought into vigorous discussion. The fine-pattern fabrication technology processing, which has been pursued as a means for realizing higher integration and higher density, has inevitably brought about higher performance and higher speed of the MOS device. Gate delay time below 1 ns, which was conventionally considered to be realized by only bi-polar devices, is now at the stage of actual application. However, considering the delay time of an MOS device, there may be included delay time at input/output portions, delay time at interconnections, etc., along with the gate delay time. The delay time at the interconnection is especially increasing with the increase in chip dimensions following larger scale integration, thus hindering the effective reduction of the total delay time for the MOS device.
Similar problems, as referred to above, are also Present in a GaAs LSI technology, which is expected to function at a speed higher than that of the Si LSI technology. Meanwhile, since the GaAs LSI is to be driven at a lower voltage and a larger current than the Si LSI technology, potential rising or falling on the interconnection due to the interconnection resistance (particularly, in the interconnection such as a power source line, etc. through which a large current flows) tends to occur, thus resulting in the deterioration of various characteristics.
Accordingly, investigation has begun into replacement of the interconnection material, from metal to a superconductive substance in which electrical resistance is reduced to zero under certain conditions.
The material currently under study for use as an interconnection material of a semiconductor is a high-temperature superconductive material (e.g. of Y-Ba-Cu-O group, etc.) having a critical temperature, in which electrical resistance becomes 0, in the vicinity of the temperature of liquid nitrogen (77K) or in a temperature region higher than that.
However, the high-temperature superconductive material as referred to above does not generally show superconductive characteristics unless it is subjected to sintering for several hours at high temperatures close to 1000.degree. C. Since active elements such as transistors and the like will have already been formed on a semiconductor substrate, heat treatment at such a high temperature is undesirable because the transistors, etc. deteriorate or become destroyed by the heat.
More specifically, in order to form interconnections for a semiconductor device of a high-temperature superconductive material with an interconnection resistance close to 0, it is necessary to lower the heat treating temperature of the material at the vapor deposition step, or thereafter. It is preferable that the heat treating temperature should be lowered to about 400.degree. C. or thereabout, although it may differ depending on the kinds of the semiconductor substrates.
Sputtering processes, MBE (Molecular Beam Epitaxy) processes, etc., which are expected to be of promise for forming a thin film of a high-temperature superconductive material over a semiconductor substrate, are extremely superior techniques with respect to alignment of crystal orientation. However, in both of these processes, since the vapor deposition is effected while the substrate is being heated at a temperature of approximately 800.degree. C., lowering of the temperature is not sufficiently achieved as desired resulting in the possibility that for transistors, etc. may be degraded or destroyed.